产品描述

74HC160D/AIP74HC160 是高速硅栅CMOS器件，与低功耗肖特基TTL (LSTTL)针脚兼容。该类器件的规格符合JEDEC标准no. 7A。

74HC/HCT160是同步可预设十进制计数器，具有内部前视进位且可用于高速计数。

The AiP74HC/HCT160 is a synchronous presettable decade counter with an internal look-ahead carry.Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PˉEˉ) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MˉRˉ) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PˉEˉ, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be

HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP))

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to